Reference: W2496
Salary: E13 (>4000 gross per month depending on experience)
Duration: 3 years
Country/Territory: Germany
Organization: Saarland University
Project: SafeSecS
More information: Link
Contact: Jan Reineke <reineke@cs.uni-saarland.de>
As part of the ERC Advanced Grant “Abstractions for Safe and Secure HW/SW Systems” (https://cordis.europa.eu/project/id/101020415) I am looking for a postdoctoral researcher. These position is fully-funded (E13/E14) and available for an initial period of three years.
The recruited candidates are expected to conduct research on the design and verification of processors with provable security (in particular w.r.t. side channel leakage) and timing-predictability properties (enabling their use in hard real-time systems). We have a track record of high-impact publications in these areas (recent papers at CAV, POPL, PLDI, RTSS, S&P, CCS, USENIX Security, including best paper awards at S&P 2021 and RTSS 2019).
The successful candidate will also be expected to:
- Course or research background in computer architecture, formal methods (e.g. verification, model checking, abstract interpretation, fuzzing, or real-time analysis), or computer security
- Strong verbal and written communication skills
- Independence and “drive” to perform research and to publish in high-impact venues
A brief overview of potential topics can be found here:
https://embedded.cs.uni-saarland.de/thesistopics.php
Please do not hesitate to contact Jan Reineke (reineke@cs.uni-saarland.de) with any questions.