Reference: W2494
Salary: E13/E14 (depending on experience, >4000 gross)
Duration: 3 years
Country/Territory: Germany
Organization: Saarland University
Project: SafeSecS
More information: Link
Contact: Jan Reineke <reineke@cs.uni-saarland.de>
As part of the ERC Advanced Grant “Abstractions for Safe and Secure HW/SW Systems” (https://cordis.europa.eu/project/id/101020415) I am looking for a postdoctoral researcher. These position is fully-funded (E13/E14) and available for an initial period of three years.
Requirements and responsibilities:
- Research on program analysis of security and/or real-time properties. We are particularly interested in microarchitectural security (cache side channels, Spectre, Meltdown, etc.) and timing predictability (cache and pipeline analysis).
- Research on the design and verification of processors with provable security (in particular w.r.t. side channel leakage) and timing-predictability properties (enabling their use in hard real-time systems).
- We have a track record of high-impact publications in these areas (recent papers at CAV, POPL, PLDI, RTSS, S&P, CCS, USENIX Security, including paper awards at CCS 2023, S&P 2021, RTSS 2018, 2019, and 2023).
The successful candidate will also be expected to:
- Research experience in computer security, formal methods, or real-time systems
- Course or research background in formal methods (e.g. verification, model checking, abstract interpretation, fuzzing, or real-time analysis), computer architecture, or computer security
- Strong verbal and written communication skills
- Independence and “drive” to perform research and to publish in high-impact venues
The particular research topic is quite flexible and will be determined based on the interests and prior experience of the candidate. Please do not hesitate to contact Jan Reineke (reineke@cs.uni-saarland.de) with any questions.