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Filipe Pacheco (Publications)

Filipe Pacheco (Publications)

Filipe Pacheco (Publications)

PhD University of Porto, Portugal
Professor, PhD Researcher

Filipe de Faria Pacheco Paulo (born Filipe de Faria Pacheco in 1971) has a degree (1994), MSc (1997) and PhD (2009) in Electrical and Computer Engineering at the University of Porto. Since 1996 he is a teaching at the Department of Computer Engineering, - School of Engineering of the Polytechnic Institute of Porto. He was researcher at the Systems and Robotics Institute, Industrial Automation Group (University of Porto), from 1994 to 1996, in the area of User Interfaces. He has worked in Multimedia and Real-Time networks projects in CISTER from 2002 and organized major scientific events. Since 2013 he is also a member of the board of directors of the unit.

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Conference or Workshop Papers/Talks
Queuing and Routing in a Hierarchical Powerline Communication System HURRAY-TR-050901 
Filipe Pacheco, Luis Miguel Pinho, Eduardo Tovar10th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA'05), IEEE. 19, Sep, 2005, 2, pp 8-66. Catania, Italy.
A Power Line Communication Stack for Metering, SCADA and Large-scale Domotic Applications HURRAY-TR-050402 
Filipe Pacheco, Marksim Lobashov, Luis Miguel Pinho, Gerhard Pratl9th International Symposium on Power-Line Communications and Its Applications (ISPLC 2005). 6, Apr, 2005, pp 61-65. Vancouver, Canada.
Technical Reports
REMPLI D4.4 - NMS Implementation HURRAY-TR-030306 
Gerd Bumiller, Filipe Pacheco29, Mar, 2005.REMPLI project deliverable.
Order of authors is not relevant in this document. Not all authors are listed.
Reviewer: J. Walocha