Hard real-time multiprocessor scheduling resilient to core failures
Ref: CISTER-TR-151105 Publication Date: 19 to 21, Aug, 2015
Hard real-time multiprocessor scheduling resilient to core failures
Ref: CISTER-TR-151105 Publication Date: 19 to 21, Aug, 2015Abstract:
Most multiprocessor scheduling theory overlooks
the possibility of hardware failures that entirely nullify the
computation carried out by a task instance, and potentially
also make the respective processor henceforth unusable. Yet,
such failures may occur, causing the system to fail. Motivated
by this reality, we introduce a new concept of hard real-time
schedulability guarantees for critical multiprocessor systems and
analysis for their derivation. Namely, all deadlines must be met,
even in the event of a core failure. A scheduling approach,
based on global fixed priorities, and accompanying analysis, for
achieving such guarantees are then formulated
Document:
21st IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2015), pp 122-131.
Hong Kong, China.
DOI:10.1109/RTCSA.2015.26.
Record Date: 27, Nov, 2015
Short links for this page: www.cister-labs.pt/docs/10_1109_rtcsa_2015_26 www.cister-labs.pt/docs/cister_tr_151105 www.cister-labs.pt/docs/1168