Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCs
Ref: CISTER-TR-180408 Publication Date: 19 to 23, Mar, 2018
Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCs
Ref: CISTER-TR-180408 Publication Date: 19 to 23, Mar, 2018Abstract:
This paper aims to reduce the pessimism of the analysis of the multi-point progressive blocking (MPB) problem in real-time priority-preemptive wormhole networks-on-chip. It shows that the amount of buffering on each network node can influence the worst-case interference that packets can suffer along their routes, and it proposes a novel analytical model that can quantify such interference as a function of the buffer size. It shows that, perhaps counter-intuitively, smaller buffers can result in lower upper-bounds on interference and thus improved schedulability. Didactic examples and large-scale experiments provide evidence of the strength of the proposed approach.
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Additional Files:
Design, Automation and Test in Europe Conference and Exhibition (DATE 2018), Track E: Embedded and Cyber-Physical Systems, pp 219-224.
Dresden, Germany.
DOI:10.23919/DATE.2018.8342006.
ISBN: 978-3-9819263-0-9.
ISSN: 1558-1101.
Notes: Best Paper Award 2018
Record Date: 17, Apr, 2018
Short links for this page: www.cister-labs.pt/docs/10_23919_date_2018_8342006 www.cister-labs.pt/docs/cister_tr_180408 www.cister-labs.pt/docs/1368