A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling
Ref: CISTER-TR-200801 Publication Date: 21 to 24, Apr, 2020
A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling
Ref: CISTER-TR-200801 Publication Date: 21 to 24, Apr, 2020Abstract:
When adopting multi-core systems for safety-critical
applications, certification requirements mandate bounding the
delays incurred in accessing shared resources. This is the case of
global memories, whose access is often regulated by memory
controllers optimized for average-case performance and not
designed to be predictable. As a consequence, worst-case bounds
on memory access delays often result to be too pessimistic,
drastically reducing the advantage of having multiple cores. This
paper proposes a fine-grained analysis of the memory contention
experienced by parallel tasks running on a multi-core platform.
To this end, an optimization problem is formulated to bound the
memory interference by leveraging a three-phase execution model
and holistically considering multiple memory transactions issued
during each phase. Experimental results show the advantage in
adopting the proposed approach on both synthetic task sets and
benchmarks.
Daniel Casini
Geoffrey NelissenEvents:
Document:
View
Download26th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2020), pp 239-252.
Online.
DOI:10.1109/RTAS48715.2020.000-3.
ISBN: 978-1-7281-5499-2.
ISSN: 2642-7346.
Record Date: 3, Aug, 2020